Semiconductor manufacturers design high performance processors (e.g., CPUs) to compete in a competitive, high-volume market. One of the key marketing features of the processors is their performance-per-watt ratio, which indicates the best performance, (fastest speed and best architecture), at the lowest possible power consumption. Having a favorable performance-per-watt ratio directly affects average selling prices and each manufacturer's profit margin. Thus, a key part of the marketing and capability of each semiconductor manufacturer is to strive for the best performance-per-watt ratio in the designs of these processors.
For a circuit designer who is performing the structured custom design style where cells, (pre-characterized circuit structures selected from a library (e.g., database) of circuit structures (e.g., gates)), are optimally placed and connected, multiple design iterations are used to improve the performance-per-watt ratio. The circuit designer typically uses a graphical user interface (GUI) to change cells to a different cell type or to insert buffer cells. The GUI may also be used to drag and drop the placement of a cell relative to the other cells.
Thus, the circuit designer combines the cells to implement logic functions for a circuit design with the most optimal power and timing. The placement of the cells may be changed, and the location of the cells may be moved around to better optimize the routing of connections between the cells by physically shortening their connections so that capacitance may be reduced, which is one of the primary power consumption considerations.
Currently, a circuit designer must use different tools to perform different circuit design functions. For example, a schematic tool may be used to show how the cells and wires of a circuit are connected, but they do not show placement information, (e.g., a circuit layout having multiple layers that shows the arrangement of the cells). In another example, a separate tool may be used to show the arrangement of the cells, but does not show the connections between the cells. Furthermore, a circuit designer may use a separate static timing analysis tool that performs a batch timing analysis of all cells and wire parasitics based on a netlist of the design, and generates a report of timing paths that indicate how fast, (i.e., the maximum clock frequency), the circuit is going to run.